nadav12_batito
New Contributor
New Contributorvhdl error
i neep to plan counter bcd library ieee; use ieee.std_logic_1164.all; entity h145 is port ( resetn: in std_logic; clk: in std_logic; sclear: in std_logic; cep, cet: in std_logic; qout: buff...
Looks like you're trying to synthesize your test bench, which makes no sense. Are you trying to synthesize or simulate? The test bench is for simulation only. Whereas for synthesis the top level should be entity h145 without the test bench.
