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Altera_Forum's avatar
Altera_Forum
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17 years ago

VHDL design no more works with Quartus 7 or 8

Quartus design who is well synthesized with quartus II v6, well compiled with Modelsim, well synthesized with xilinx ise, have errors in synthesis with quartus v7 or v8.

This is a pic model carried in a stratix chip.

errors messages are: Error: Illegal directional connection from the node "P16F84:P1|PPX_Port:porta|Data_Out[0]" to the node "P16F84:P1|PPX16:ppx|PPX_ALU:alu|Q[1]"

I thing that quartus find a conflict between some ram and other bus.

Thanks for your ideas

Patxinou

All files in attachments

Top file : pic.vhd

Top entity : pic

pin assignement in: startiw_pin_assign.tcl

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    The problem comes from feeding Op_Bus to PPX_ALU input A. If you replace it e. g. by a constant driver, the project can be compiled. I'm not motivated to trace the various internal three-state busses in the design to see, if the logic definition may be ambiguous or if the code actually reveals a Quartus bug. I guess, that the problem can be avoided by cutting one of the busses by a multiplexer. But this implies to understand the dataflow and the three-state enable conditions before.

    I also verified, that the design can be compiled with Quartus 6.0SP1.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    I want to ask that do you have the solution to the problem? If you solute it, can you tell me the answer to deal with it? Thanks!