VHDL design no more works with Quartus 7 or 8

The problem comes from feeding Op_Bus to PPX_ALU input A. If you replace it e. g. by a constant driver, the project can be compiled. I'm not motivated to trace the various internal three-state busses in the design to see, if the logic definition may be ambiguous or if the code actually reveals a Quartus bug. I guess, that the problem can be avoided by cutting one of the busses by a multiplexer. But this implies to understand the dataflow and the three-state enable conditions before.