Forum Discussion
7 Replies
- Altera_Forum
Honored Contributor
your 6 bit number is binary, which is also hex.
Your questions doesnt really make much sense. (you need 7 bits to represent 100 in binary) 100 in binary is 1100100 (which is 0x64 in hex). - Altera_Forum
Honored Contributor
100 what? Please explain your problem more clearly.
With 6 bits, you cannot represent 100. - Altera_Forum
Honored Contributor
Do you really need a 0-100 output? that will be a 7 bit output.
the formula will be: OP = n/32 * 100 - Altera_Forum
Honored Contributor
--- Quote Start --- Yes that's exactly what i am trying to say. But how i can make this convert in vhdl? (in structural) I want to show the 7 bits (100) in modelsim. --- Quote End --- multiply your value by 100 first then discard 5 lsbs from result - Altera_Forum
Honored Contributor
--- Quote Start --- actually the value must be divided by 32 and after multiply with 100? how i can multiply in vhdl? i am begginer. --- Quote End --- no first multiply then divide (the opposite is correct in theory and equivalent but difficult to implement) multiply using instant of lpm mult or just the operator * but convert to correct type e.g. result <= unsigned(value) * 100; -- 6 bits * 7 bits => 13 bits result_final <= result(12 downto 5); - Altera_Forum
Honored Contributor
--- Quote Start --- ok! so if i use this two lines i can convert my number? where you say the word value is the variable of the 6 bit number? another question is there any other way for example 6 bit binary to bcd? because i don't know if it is structural for example the symbol * we didn't use it yet --- Quote End --- if your table is just this: 32 => 100 24 => 75 16 => 50 8 => 25 0 => 0 then all you need is just piece of logic (no mult or div). otherwise use * and see binary to bcd ? what is the connection to your post? - Altera_Forum
Honored Contributor
so do what I suggested.
your value of 6 bits range is 0~32 call it val (std_logic_vector(5 downto 0); result to be unsigned(12 downto 0); final_res to be std_logic_vector(6 downto 0); result <= unsigned(val)*100; final_res_hopefully_in_binary <= std_logic_vector(result(11 downto 5));