vhdl code conversion need help

so do what I suggested.

your value of 6 bits range is 0~32 call it val (std_logic_vector(5 downto 0);

result to be unsigned(12 downto 0);

final_res to be std_logic_vector(6 downto 0);

result <= unsigned(val)*100;

final_res_hopefully_in_binary <= std_logic_vector(result(11 downto 5));