New ContributorVHDL Aggregate Error
I keep getting this error, Error (10514): VHDL aggregate error : can't determine type of aggregate -- found 6 possible types
What should I do? Thanks!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity final_game01 is
port ( enable : in std_logic;
clk : in std_logic;
-- score0, score1 : out std_logic_vector (6 downto 0);
LED: out std_logic_vector (8 downto 0)
);
end entity;
architecture lab of final_game01 is
signal time_count, count, count2: integer:=0;
signal cake : std_logic;
begin
process (clk, enable)--code for FF/MOD
begin
If (enable='1') then
time_count<=0;
cake<='0';
Elsif rising_edge (clk) then
If (time_count = 4999999) then
cake<= NOT cake;
time_count<=0;
Else
time_count<= time_count+1;--MOD count up
End If;
End If;
If (enable='1') then--when r is 0 the count will reset at 0
count <=0;
Elsif (rising_edge (cake)) then
If (count = 0) then--0
count<=9;--9
Else
count<=count+1;
End if;
If (count2 = 0) then--0
count2<=13;--13
Else
count2<=count2+1;
End If;
End if;
case (count, count2) is
when (count = 0 and count2 = 0) =>
LED(0)<='1';
when (count = 1 and count2 = 1) =>
LED(1)<='1';
when (count = 2 and count2 = 2) =>
LED(2)<='1';
when (count = 3 and count2 = 3) =>
LED(3)<='1';
when (count = 4 and count2 = 4) =>
LED(4)<='1';
when (count = 5 and count2 = 5) =>
LED(5)<='1';
when (count = 6 and count2 = 6) =>
LED(6)<='1';
when (count = 7 and count2 = 7) =>
LED(7)<='1';
when (count = 8 and count2 = 8) =>
LED(8)<='1';
end case;
End process;
End architecture;
