VHDL Aggregate Error

It's hard to tell with the formatting, but you have two if statements in the process with the same if check at the same level: If (enable='1'). Perhaps one or the other of these checks should be if (enable='0').

I put the process in code tags to make it slightly easier to read below.

Also, you put enable in the sensitivity list, which makes it function as an asynchronous reset instead of an enable signal, which is usually synchronous. I don't know if that's what you're intending.

As far as the aggregate error is concerned, the only aggregate I see is in your case statement which doesn't look like it should be an issue. Usually the error points to a line number, so I don't know if there's other code missing here or what.

#iwork4intel

process (clk, enable)--code for FF/MOD
 begin
  If (enable='1') then
   time_count<=0;
   cake<='0';
  Elsif rising_edge (clk) then
   If (time_count = 4999999) then
    cake<= NOT cake;
    time_count<=0;
   Else
    time_count<= time_count+1;--MOD count up
   End If;
  End If;
 
 If (enable='1') then--when r is 0 the count will reset at 0
    count <=0;
   Elsif (rising_edge (cake)) then
     If (count = 0) then--0
      count<=9;--9
     Else
      count<=count+1;
     End if;
  
    If (count2 = 0) then--0
      count2<=13;--13
     Else
      count2<=count2+1; 
     End If;
  End if;
  
 case (count, count2) is
   when (count = 0 and count2 = 0) =>
    LED(0)<='1';
   when (count = 1 and count2 = 1) =>
    LED(1)<='1';
   when (count = 2 and count2 = 2) =>
    LED(2)<='1';
   when (count = 3 and count2 = 3) =>
    LED(3)<='1';
   when (count = 4 and count2 = 4) =>
    LED(4)<='1';
   when (count = 5 and count2 = 5) =>
    LED(5)<='1';
   when (count = 6 and count2 = 6) =>
    LED(6)<='1';
   when (count = 7 and count2 = 7) =>
    LED(7)<='1';
   when (count = 8 and count2 = 8) =>
    LED(8)<='1';
  end case;
  End process;