I have recently started using the basic new features of VHDL 2008, and they compile fine in my version of Aldec Active HDL, but do not in Quartus. For example, the basic process: process(MCLK,HRST) begin if (HRST = '1') then reg <= '0'; elsif rising_edge(MCLK) then reg <= input; end if; end process; can be rewritten in VHDL 2008 as: process(MCLK,HRST) begin if HRST: reg <= '0'; elsif rising_edge(MCLK) then reg <= input; end if; end process; there are several enhancements in VHDL 2008 to reduce verbosity; and I am just trying to find a thread, white paper, or link somewhere that explicity states the VHDL 2008 supported features in Quartus 10. What would be nice is a app note by Altera that maybe takes one of Jim Lewis Synthworks white papers and elaborates on whether those features in VHDL 2008 are covered in Quartus 10. Thanks, James

are you sure you dont need the "then" at the end of an if? I thought you had to use the new conditional operator to convert std_logic to a boolean: if ?? HRST then ..etc But anyway, the VHDL 2008 supported features are in the quartus manual 10, section 9-10 - VHDL 2008 Support. As copied from the manual: The Quartus II software supports the following VHDL 2008 functions: &#9632; Block comments &#9632; Simplified sensitivity lists &#9632; Extensions to generate &#9632; Matching case statement &#9632; Matching equality/inequality operators &#9632; Enhanced bit string literals &#9632; Unconstrained elements in arrays So nowhere near the full list!

When using a conditional in an IF statement, the ?? is not required. From the Doulos website: """VHDL-2008 introduces a new operator, ??. It ’s called the condition operator and it converts a STD_LOGIC expression to a BOOLEAN one: '1' and 'H' are considered TRUE and everything else FALSE. (It also converts BIT to BOOLEAN .) So you can now write this: if ?? A and B then ... or, even better ... In certain circumstances, ?? is applied implicitly. The condition expression of an if statement is one of those. So you can indeed now write: if A and B then ...""" Technically, in my code that I initially listed, I left out the THEN in the line: if HRST then: I had the THEN statement in my code, just didn't copy it. This compiles fine in Aldec HDL where VHDL 2008 is checked as the language version. I am trying to find out if Quartus needs the ?? or can discern that that the bit literal should be TRUE.

Given the supported features, no it doesnt. Im sure Ive accidently left std_logics without an = in some recent code, and it didnt work. Until it has full 2008 support, it might be safer to stick with 93 for now.

On a similar note: Does the Altera Modelsim support VHDL-2008? Can't find any mention of it in the Modelsim docs.

Not in any useful capacity. It has the VHDL 93 version of the fixed point libraries, but thats about it. Quartus has better 2008 support than Modelsim. Apparently, Almost full VHDL 2008 support for modelsim comes with modelsim 6.7 and 6.8

Altera_Forum

Honored Contributor

15 years ago

Vhdl 2008

I have recently started using the basic new features of VHDL 2008, and they compile fine in my version of Aldec Active HDL, but do not in Quartus. For example, the basic process:

process(MCLK,HRST)

begin

if (HRST = '1') then

reg <= '0';

elsif rising_edge(MCLK) then

reg <= input;

end if;

end process;

can be rewritten in VHDL 2008 as:

process(MCLK,HRST)

begin

if HRST:

reg <= '0';

elsif rising_edge(MCLK) then

reg <= input;

end if;

end process;

there are several enhancements in VHDL 2008 to reduce verbosity; and I am just trying to find a thread, white paper, or link somewhere that explicity states the VHDL 2008 supported features in Quartus 10. What would be nice is a app note by Altera that maybe takes one of Jim Lewis Synthworks white papers and elaborates on whether those features in VHDL 2008 are covered in Quartus 10.

Thanks,

James

20 Replies

Altera_Forum
Honored Contributor
15 years ago
are you sure you dont need the "then" at the end of an if? I thought you had to use the new conditional operator to convert std_logic to a boolean:

if ?? HRST then
..etc

But anyway, the VHDL 2008 supported features are in the quartus manual 10, section 9-10 - VHDL 2008 Support.

As copied from the manual:

The Quartus II software supports the following VHDL 2008 functions:
■ Block comments
■ Simplified sensitivity lists
■ Extensions to generate
■ Matching case statement
■ Matching equality/inequality operators
■ Enhanced bit string literals
■ Unconstrained elements in arrays

So nowhere near the full list!
Altera_Forum
Honored Contributor
15 years ago
When using a conditional in an IF statement, the ?? is not required. From the Doulos website:

"""VHDL-2008 introduces a new operator, ??. It ’s called the condition operator and it converts a STD_LOGIC expression to a BOOLEAN one: '1' and 'H' are considered TRUE and everything else FALSE. (It also converts BIT to BOOLEAN .) So you can now write this:
if ?? A and B then
...
or, even better ...
In certain circumstances, ?? is applied implicitly. The condition expression of an if statement is one of those. So you can indeed now write:
if A and B then
..."""

Technically, in my code that I initially listed, I left out the
THEN in the line:

if HRST then:

I had the THEN statement in my code, just didn't copy it.
This compiles fine in Aldec HDL where VHDL 2008 is checked
as the language version.

I am trying to find out if Quartus needs the ?? or can discern
that that the bit literal should be TRUE.
Altera_Forum
Honored Contributor
15 years ago
Given the supported features, no it doesnt.

Im sure Ive accidently left std_logics without an = in some recent code, and it didnt work.

Until it has full 2008 support, it might be safer to stick with 93 for now.
Altera_Forum
Honored Contributor
15 years ago
On a similar note:

Does the Altera Modelsim support VHDL-2008? Can't find any mention of it in the Modelsim docs.
Altera_Forum
Honored Contributor
15 years ago
Not in any useful capacity. It has the VHDL 93 version of the fixed point libraries, but thats about it. Quartus has better 2008 support than Modelsim. Apparently, Almost full VHDL 2008 support for modelsim comes with modelsim 6.7 and 6.8
Altera_Forum
Honored Contributor
15 years ago
Thank you. Tried taking advantage of some of the cleaner syntax for base specifiers in constants and it took me longer than I care to admit to realize that this boiled down to VHDL-2008 support.
Altera_Forum
Honored Contributor
11 years ago
Based on my experiment, I found out Quartus II 14.x does not support hierarchical signals. Can anyone confirm this? Thank u
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
Based on my experiment, I found out Quartus II 14.x does not support hierarchical signals. Can anyone confirm this? Thank u
--- Quote End ---

I can confirm this. But why would they want to support them? they are meant for simulation only.
Altera_Forum
Honored Contributor
11 years ago
Can I use hierarchical signals to port out nets / signals in the lower level? Is there other easy way (s) to do that in VHDL. For example, I have three levels in my design. Instead of carrying large number of IO through hierarchy, I can use hierarchical signals to port them to the top level for board level debugging? Thank u
Altera_Forum
Honored Contributor
11 years ago
No. You will need to bring them to a pin.

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Vhdl 2008

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