VGA monitor

Hi Tricky.

Here is the code. Thanks.

library ieee;

use ieee.std_logic_1164.all;

entity vga_test is

port( clk, reset: in std_logic;

sw: in std_logic_vector(2 downto 0);

hsync, vsync, comp_sync: out std_logic;

rgb: out std_logic_vector(2 downto 0));

end vga_test;

architecture arch of vga_test is

signal rgb_reg: std_logic_vector(2 downto 0);

signal video_on: std_logic;

begin -- instantiate VGA sync circuit

vga_sync_unit: entity work.vga_sync

port map(clk=>clk, reset=>reset, hsync=>hsync,

vsync=>vsync, comp_sync=>comp_sync,

video_on=>video_on,

p_tick=>open, pixel_x=>open,

pixel_y=>open);

process(clk, reset) -- rgb buffer

begin

if (reset = '1') then

rgb_reg <= (others => '0');

elsif (clk' event and clk = '1') then

rgb_reg <= sw;

end if;

end process;

rgb <= rgb_reg when video_on = '1' else "000";

end arch;

What about the vga sync entity?

Have to simulated the design? Did it behave s you expected with the correct timings when you simulated it? I'd you didn't simulate, why not?

Hi Daixiwen,

Thanks for your reply. Here is my vga_sync entity. Whenever I download the program into fpga, my VGA monitor is going to sleep mode. Why this happen? Thanks for your help.

VGA SYNC:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity vga_sync is

port (clk,reset: in std_logic;

hsync,vsync: out std_logic;

video_on, p_tick: out std_logic;

pixel_x, pixel_y: out std_logic_vector (9 downto 0));

end vga_sync;

architecture arch of vga_sync is

--VGA 640-by-480 sync parameters

constant HD: integer:=640;

constant HF: integer:=16;

constant HB: integer:=48;

constant HR: integer:=96;

constant VD: integer:=480;

constant VF: integer:=10;

constant VB: integer:=33;

constant VR: integer:=2;

--mod-2 counter

signal mod2_reg,mod2_next:std_logic;

--sync counter

signal v_count_reg, v_count_next: unsigned (9 downto 0);

signal h_count_reg, h_count_next: unsigned (9 downto 0);

--output buffer

signal v_sync_reg, h_sync_reg: std_logic;

signal v_sync_next, h_sync_next:std_logic;

--status signal

signal h_end, v_end, pixel_tick: std_logic;

begin

--register

process (clk,reset)

begin

if reset='1' then

mod2_reg <= '0';

v_count_reg <= (others=> '0');

h_count_reg <= (others=> '0');

v_sync_reg <= '0';

h_sync_reg <= '0';

elsif (clk' event and clk='1') then

mod2_reg <= mod2_next;

v_count_reg <=v_count_next;

h_count_reg <=h_count_next;

v_sync_reg <=V_sync_next;

h_sync_reg <=h_sync_next;

end if;

end process;

--mod-2 circuit to generate 25MHz enable tick

mod2_next <= not mod2_reg;

--25MHz pixel tick

pixel_tick <= '1' when mod2_reg='1' else '0';

--status

h_end <= --end of horizontal center

'1'when h_count_reg=(HD+HF+HB+HR-1) else --799

'0';

v_end <=--end of vertical

'1'when h_count_reg=(VD+VF+VB+VR-1) else --799

'0';

--mod -800 horizontal sync counter

process (h_count_reg,h_end,pixel_tick)

begin

if pixel_tick='1'then

if h_end ='1' then

h_count_next <= (others=>'0');

else

h_count_next <= h_count_reg + 1;

end if ;

else

h_count_next <= h_count_reg;

end if ;

end process;

-- mod-525 vertical sync counter

process (v_count_reg,v_end,pixel_tick)

begin

if pixel_tick='1'then

if v_end = '1' then

v_count_next <= (others=>'0');

else

v_count_next <= v_count_reg + 1;

end if;

else

v_count_next <= v_count_reg;

end if;

end process;

-- horizontal and vertical sync, buffered to avoid glitch

h_sync_next <=

'1' when (h_count_reg>=(HD+HF)) --656

and (h_count_reg<=( HD+HF+HR-1 )) else --751

'0';

v_sync_next <= '1' when (v_count_reg>=(VD+VF))--490

and (v_count_reg<=( VD+VF+VR-1 )) else --491

'0';

--video on/off

video_on <=

'1' when (h_count_reg<HD) and (v_count_reg<VD) else

'0';

--output signal

hsync <=h_sync_reg;

vsync <=v_sync_reg;

pixel_x <=std_logic_vector (h_count_reg);

pixel_y <=std_logic_vector (v_count_reg);

p_tick <=pixel_tick;

end arch;

Here is my top level. VGA TEST

library ieee;

use ieee.std_logic_1164.all;

entity vga_test is

port( clk, reset: in std_logic;

sw: in std_logic_vector(7 downto 0);

hsync, vsync: out std_logic;

red,green,blue: out std_logic_vector(7 downto 0));

end vga_test;

architecture arch of vga_test is

signal red_reg: std_logic_vector(7 downto 0);

signal green_reg: std_logic_vector(7 downto 0);

signal blue_reg: std_logic_vector(7 downto 0);

signal video_on: std_logic;

begin -- instantiate VGA sync circuit

vga_sync_unit: entity work.vga_sync

port map(clk=>clk, reset=>reset, hsync=>hsync,

vsync=>vsync, video_on=>video_on,

p_tick=>open, pixel_x=>open,

pixel_y=>open);

process(clk, reset) -- rgb buffer

begin

if (reset = '1') then

red_reg <= (others => '0') ;

green_reg <= (others => '0') ;

blue_reg <= (others => '0') ;

elsif (clk' event and clk = '1') then

red_reg <= sw;

green_reg <= sw;

blue_reg <= sw;

end if;

end process;

red <= red_reg when video_on = '1' else (others => '0');

green <= green_reg when video_on = '1' else (others => '0');

blue <= blue_reg when video_on = '1' else (others => '0');

end arch;