Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

very strange QuartusII 7.1 synthesis Tool results

Hello everyone,

I have created a project using Quartus II 7.1 with the attached files. And the top level module name is TOP.

The files are APBM.v, APBS1.v, APBS2.v, APBS3.v, ARBITER.v, MuxS2M.v, TOP.v

The following line is from MuxS2M.v

when using

case ({PSELS3,PSELS2,PSELS1}) produces worst results ALUT's (1440)

when using

case ({PSELS1,PSELS3,PSELS2}) produces better results ALUT's (1424)

when using

case ({PSELS2,PSELS1,PSELS3}) produces best results ALUT's (977)

in principle APBS1, APBS2, APBS3 must use the same amount of resources, but by using the

above case statements, they use different amount of resources.

I have optimized the design for Area.

So my question is:

1) Am I missing something

2) Is it a bug from Quartus

3) I tried the same design in Xilinx ISE, for all of the cases, i get the same amount of LUT usage.

Eagerly waiting for some replies.

Regards,

Anil

13 Replies

Show More
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Your files are the same on Quartus 7.2, I don't have a 7.1 anymore. It's going to be a little volatile, because the edit isn’t fixing the underlying redundancy. It just put the signals on a platter for synthesis to find.

    To think about heuristic minimization – Heuristic means that the synthesis tool is going to take a quick look at the design for things to minimize. If it sees the redundancy you get a bonus. If it doesn’t you’re no worse off than you came in. The best to worst spread here is the difference between finding all the redundancy and none of it.

    What’s the target application? You can probably get smaller and faster if some of these requirements can be tweaked. Tweak it enough and you can get into RAM, which sounds like the way to go personally.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Hi gsynth,

    Actually it is not a real project. I was trying to learn some system verilog basics. So i built the small APB system. And then synthesized the design. later i translated to verilog, to see if system verilog was producing the same results.

    In end effect, i saw that both are producing the same results.

    never the less, i will try to use Quartus II 7.2 and see how i can figure out the issues. My only idea is to get more learning practice and learn some tricks to get better results.

    Regards,

    Anil
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    For your experiments / entertainment - attached reg_file.v

    As it turns out it isn't easy to get synthesis to do just one clock enable for the whole register file. I think this mapping is the best use of the cells. You could turn the synchronous reset into a synchronous constant load for 'free'.

    The unique clock enable per register word is OK on this small scale, but seems iffy to me as the chip fills.

    With System Verilog you could turn those generate loops into arrays.