very strange QuartusII 7.1 synthesis Tool results

For your experiments / entertainment - attached reg_file.v

As it turns out it isn't easy to get synthesis to do just one clock enable for the whole register file. I think this mapping is the best use of the cells. You could turn the synchronous reset into a synchronous constant load for 'free'.

The unique clock enable per register word is OK on this small scale, but seems iffy to me as the chip fills.

With System Verilog you could turn those generate loops into arrays.