Forum Discussion
Altera_Forum
Honored Contributor
18 years agoHi gsynth,
Actually it is not a real project. I was trying to learn some system verilog basics. So i built the small APB system. And then synthesized the design. later i translated to verilog, to see if system verilog was producing the same results. In end effect, i saw that both are producing the same results. never the less, i will try to use Quartus II 7.2 and see how i can figure out the issues. My only idea is to get more learning practice and learn some tricks to get better results. Regards, Anil