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Altera_Forum's avatar
Altera_Forum
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15 years ago

verilog simulation model issue of altpll in Straitx IV device

Does anybody meet this case as below?

I'm using Stratix IV for one project and I use the on chip PLL of device to generate high clock for our system. I simulate my design with Cadence ncverilog tool. When I run the simulation to FPGA version code ( a lot of altera memories and PLL model ), the simulation is very slow. While I run the ASIC version simulation, it's quick. I tried to disable the PLL verilog model and use a simple one, and it's fast now.

Is there any option we need to configure when we use PLL verilog simulation model?

Thanks

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I hear about users writing their own PLL simulation models quite a bit(I don't have one handy to post though). Bottom line is that it has a lot of activity to mimic how a PLL works, when most users want the simplest/quickest model possible. Hopefully Altera does some improvements on this(both in PLL and transceivers) where the user can select from multiple simulation models depending on their sim goals, but I believe what you're doing is a good solution used by many.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Hi,

    I have the same issue. What is this asic version of pll simulation model.

    Can some expert point me to a lightweight simulation model for the PLL.

    I can write my own clock generator but it is not the same as verifying with

    a programmable PLL sim. model

    Thanks!