verilog simulation model issue of altpll in Straitx IV device

I hear about users writing their own PLL simulation models quite a bit(I don't have one handy to post though). Bottom line is that it has a lot of activity to mimic how a PLL works, when most users want the simplest/quickest model possible. Hopefully Altera does some improvements on this(both in PLL and transceivers) where the user can select from multiple simulation models depending on their sim goals, but I believe what you're doing is a good solution used by many.