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Altera_Forum
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15 years ago

verilog simulation model issue of altpll in Straitx IV device

Does anybody meet this case as below? I'm using Stratix IV for one project and I use the on chip PLL of device to generate high clock for our system. I simulate my design with Cadence ncverilo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi,

I have the same issue. What is this asic version of pll simulation model.

Can some expert point me to a lightweight simulation model for the PLL.

I can write my own clock generator but it is not the same as verifying with

a programmable PLL sim. model

Thanks!