Verilog sequential code

Unfortunately it is not.

The correct way to define a FF is:

always -at-(posedge CK or negedge R)

begin

if (!R)

begin

D1 <= 0;

end

else

begin

D1 <= D0;

end

end

Using blockng assignment (= instead of <=), when using multiple FF as in a shift register, results in random behavior and race conditions.

hello .

am running verilog code and the same error keep showing up ,

errors :

Error (10028): Can't resolve multiple constant drivers for net "hazard" at design1.v(159)

Error (10029): Constant driver at design1.v(138)

Error (10028): Can't resolve multiple constant drivers for net "sample" at design1.v(159)

Error: Can't elaborate top-level user hierarchy

Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 5 warnings

Error: Peak virtual memory: 181 megabytes

Error: Processing ended: Tue Apr 20 13:20:20 2010

Error: Elapsed time: 00:00:02

Error: Total CPU time (on all processors): 00:00:01

Error: Quartus II Full Compilation was unsuccessful. 6 errors, 5 warnings http://www.alteraforum.com/forum//pr...c/progress.gif (http://www.alteraforum.com/forum//proweb/misc/progress.gif)

this is the code ;

module design1 (

clock ,

reset ,

hazard ,

pulse

); // End of port list

//-------------Input Ports-----------------------------

input clock ;

input reset ;

input pulse ;

//-------------Output Ports----------------------------

output hazard ;

//-------------Input ports Data Type-------------------

// By rule all the input ports should be wires

wire clock ;

wire reset ;

//-------------Output Ports Data Type------------------

// Output port can be a storage element (reg) or a wire

reg [15:0] pulse_cntr;

reg pulse_reset;

reg [15:0] period_cntr;

reg [15:0] sample_value;

reg sample;

reg [23:0] result, result_ns;

reg [23:0] vt;

reg hazard;

initial begin

hazard = 1'b0 ;

end

always @ ( sample_value ) begin

result_ns = sample_value * 4'hc;

case ( result )

24'h00006c: vt = 24'hcccccc;

24'h0186A0: vt = 24'h007530;

24'h030D40: vt = 24'h00EA60;

24'h0493E0: vt = 24'h01ADB0;

24'h061A80: vt = 24'h020F58;

24'h07A120: vt = 24'h029810;

24'h0927C0: vt = 24'h030D20;

24'h0AAE60: vt = 24'h038270;

24'h0C3500: vt = 24'h041EB0;

24'h0DBBA0: vt = 24'h04BAF0;

24'h0F4240: vt = 24'h053020;

24'h10C8E0: vt = 24'h05CC60;

24'h124F80: vt = 24'h064190;

24'h13D620: vt = 24'h0704E0;

24'h155CC0: vt = 24'h077A10;

24'h16E360: vt = 24'h07EF40;

24'h186A00: vt = 24'h086470;

24'h19F0A0: vt = 24'h0927C0;

24'h1B7740: vt = 24'h099CF0;

24'h1CFDE0: vt = 24'h0A6040;

24'h1E8480: vt = 24'h0AFC80;

24'h200B20: vt = 24'h0B4AA0;

24'h2191C0: vt = 24'h0C0DF0;

24'h231860: vt = 24'h0CAA30;

24'h249F00: vt = 24'h0D1F60;

24'h2625A0: vt = 24'h0DE2B0;

24'h27AC40: vt = 24'h0EF7E0;

24'h2932E0: vt = 24'h0EF420;

24'h2AB980: vt = 24'h0F9060;

24'h2C4020: vt = 24'h102CA0;

24'h2DC6C0: vt = 24'h10EFF0;

24'h2F4D60: vt = 24'h116F20;

24'h30D400: vt = 24'h120160;

24'h325AA0: vt = 24'h12C4B0;

24'h33E140: vt = 24'h1360F0;

24'h3567E0: vt = 24'h13D620;

24'h36EE80: vt = 24'h149970;

24'h387520: vt = 24'h1535B0;

24'h39FBC0: vt = 24'h15D1F0;

24'h3B8260: vt = 24'h169540;

24'h3D0900: vt = 24'h1731A0;

24'h3E8F9F: vt = 24'h17A6B0;

24'h401640: vt = 24'h1842F0;

24'h419CE0: vt = 24'h190640;

24'h43237F: vt = 24'h19A280;

24'h44AA20: vt = 24'h1A65D0;

24'h4630C0: vt = 24'h1ADB00;

24'h47B760: vt = 24'h1B7740;

24'h493E00: vt = 24'h1C3A90;

24'h4AC4A0: vt = 24'h1CD6D0;

24'h4C4B40: vt = 24'h1D7310;

24'h4DD1E0: vt = 24'h1E3660;

24'h4F5880: vt = 24'h1ED2A0;

24'h50DF20: vt = 24'h1F95EF;

24'h5265C0: vt = 24'h203230;

24'h53EC60: vt = 24'h20A760;

24'h557300: vt = 24'h2191C0;

24'h56F9A0: vt = 24'h222E00;

24'h588040: vt = 24'h22F150;

24'h5A06E0: vt = 24'h238D90;

24'h5B8D80: vt = 24'h2450E0;

24'h5D1420: vt = 24'h243610;

24'h5E9AC0: vt = 24'h258960;

24'h602160: vt = 24'h264CB0;

24'h61A800: vt = 24'h271000;

24'h632EA0: vt = 24'h27AC40;

24'h64B540: vt = 24'h282170;

24'h663BE0: vt = 24'h290BD0;

24'h67C280: vt = 24'h29CF20;

24'h694920: vt = 24'h2A6B60;

24'h6ACFC0: vt = 24'h2B07A0;

24'h6C5660: vt = 24'h2BCAF0;

24'h6DDD00: vt = 24'h2CB550;

24'h6F63A0: vt = 24'h2D5190;

24'h70EA40: vt = 24'h2F4D60;

24'h7270E0: vt = 24'h2EB120;

24'h73F780: vt = 24'h2F7470;

24'h757E20: vt = 24'h2FE9A0;

24'h7704C0: vt = 24'h30ACF0;

24'h788B60: vt = 24'h317040;

24'h7A1200: vt = 24'h320C80;

default : vt = 24'h0000;

endcase

if ( result_ns <= vt )

hazard = 1;

else

hazard = 0;

end

// Pulse Counter

always @(posedge pulse or posedge reset) begin

if ( reset == 1'b1 ) begin

sample_value <= 0;

pulse_cntr <=0;

hazard = 0 ;

end

else if (sample == 1)

begin

sample_value <= pulse_cntr+1;

pulse_cntr <= 0;

sample <= 0;

end

else

begin

pulse_cntr <= pulse_cntr + 1;

end

end

// Period counter

always @(posedge clock or posedge reset) begin

if (reset == 1'b1)

begin

period_cntr <= 0;

sample <= 0;

hazard = 0 ;

end

else if ( period_cntr == 16'h000f)//557300

begin

period_cntr <= 16'h0000;

sample <= 1;

end

else

begin

period_cntr <= period_cntr + 1;

end

end

always @(posedge clock or posedge reset) begin

if (reset == 1'b1)// begin

result <= 0;

else

result <= result_ns ;

end

endmodule // End of Module design

1)

initial begin

hazard = 1'b0 ;

end

You cannot use initial for designing a circuit.

It is only useful for testbench.

2)

else if (sample == 1)

begin

sample_value <= pulse_cntr+1;

pulse_cntr <= 0;

sample <= 0;

This circuit wants to put sample at 0 when sample is 1? Which circuit can do this?

For Beginner:

I think you are using HDL as if you were programming in C or other similar languages.

Actually in Verilog every 'always' block executes indipendently whenever the specified condition is true.

So you are making multiple assignments to the same signal/register; besides, your code won't work as you expect.

Still no reply.

I'll try to see if this has been corrected in the new 10.0 release of the QuartusII software

--- Quote Start ---

Still no reply.

I'll try to see if this has been corrected in the new 10.0 release of the QuartusII software

--- Quote End ---

Hi,

your problem is that you try to set some reg ( hazard, sample ) in different processes.

You have to put them together in one.

module design1 (

clock ,

reset ,

hazard ,

pulse

); // End of port list

//-------------Input Ports-----------------------------

input clock ;

input reset ;

input pulse ;

//-------------Output Ports----------------------------

output hazard ;

//-------------Input ports Data Type-------------------

// By rule all the input ports should be wires

wire clock ;

wire reset ;

//-------------Output Ports Data Type------------------

// Output port can be a storage element (reg) or a wire

reg [15:0] pulse_cntr;

reg pulse_reset;

reg [15:0] period_cntr;

reg [15:0] sample_value;

reg sample;

reg [23:0] result, result_ns;

reg [23:0] vt;

reg hazard;

initial begin

hazard = 1'b0 ;

end

always @ ( sample_value ) begin

result_ns = sample_value * 4'hc;

case ( result )

24'h00006c: vt = 24'hcccccc;

...

...

24'h7A1200: vt = 24'h320C80;

default : vt = 24'h0000;

endcase

if ( result_ns <= vt )

hazard = 1;

else

hazard = 0;

end

// Pulse Counter

always @(posedge pulse or posedge reset) begin

if ( reset == 1'b1 ) begin

sample_value <= 0;

pulse_cntr <=0;

hazard = 0 ;end

else if (sample == 1)

begin

sample_value <= pulse_cntr+1;

pulse_cntr <= 0;

sample <= 0;

end

else

begin

pulse_cntr <= pulse_cntr + 1;

end

end

// Period counter

always @(posedge clock or posedge reset) begin

if (reset == 1'b1)

begin

period_cntr <= 0;

sample <= 0;

hazard = 0 ;end

else if ( period_cntr == 16'h000f)//557300

begin

period_cntr <= 16'h0000;

sample <= 1;

end

else

begin

period_cntr <= period_cntr + 1;

end

end

always @(posedge clock or posedge reset) begin

if (reset == 1'b1)// begin

result <= 0;

else

result <= result_ns ;

end

endmodule // End of Module design

Kind regards

GPK

--- Quote Start ---

Hi,

your problem is that you try to set some reg ( hazard, sample ) in different processes.

You have to put them together in one.

module design1 (

clock ,

reset ,

hazard ,

pulse

); // End of port list

//-------------Input Ports-----------------------------

input clock ;

input reset ;

input pulse ;

//-------------Output Ports----------------------------

output hazard ;

//-------------Input ports Data Type-------------------

// By rule all the input ports should be wires

wire clock ;

wire reset ;

//-------------Output Ports Data Type------------------

// Output port can be a storage element (reg) or a wire

reg [15:0] pulse_cntr;

reg pulse_reset;

reg [15:0] period_cntr;

reg [15:0] sample_value;

reg sample;

reg [23:0] result, result_ns;

reg [23:0] vt;

reg hazard;

initial begin

hazard = 1'b0 ;

end

always @ ( sample_value ) begin

result_ns = sample_value * 4'hc;

case ( result )

24'h00006c: vt = 24'hcccccc;

...

...

24'h7A1200: vt = 24'h320C80;

default : vt = 24'h0000;

endcase

if ( result_ns <= vt )

hazard = 1;

else

hazard = 0;

end

// Pulse Counter

always @(posedge pulse or posedge reset) begin

if ( reset == 1'b1 ) begin

sample_value <= 0;

pulse_cntr <=0;

hazard = 0 ;end

else if (sample == 1)

begin

sample_value <= pulse_cntr+1;

pulse_cntr <= 0;

sample <= 0;

end

else

begin

pulse_cntr <= pulse_cntr + 1;

end

end

// Period counter

always @(posedge clock or posedge reset) begin

if (reset == 1'b1)

begin

period_cntr <= 0;

sample <= 0;

hazard = 0 ;end

else if ( period_cntr == 16'h000f)//557300

begin

period_cntr <= 16'h0000;

sample <= 1;

end

else

begin

period_cntr <= period_cntr + 1;

end

end

always @(posedge clock or posedge reset) begin

if (reset == 1'b1)// begin

result <= 0;

else

result <= result_ns ;

end

endmodule // End of Module design

Kind regards

GPK

--- Quote End ---

Thanks Pletz but my comment of no replies refers to the original thread question.

The problem with the code is an off topic addition.

The original problem was that QuartusII Create HDL command uses blcking assignment to describe Flip flops. This causes simulation errating behaviour.