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Altera_Forum's avatar
Altera_Forum
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15 years ago

Verilog sequential code

I have a shift register made with DFF flip flops. When using the command "create HDL file for current files" the DFF are synthesized using blocking assignments as: always -at-(posedge CK or ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

For Beginner:

I think you are using HDL as if you were programming in C or other similar languages.

Actually in Verilog every 'always' block executes indipendently whenever the specified condition is true.

So you are making multiple assignments to the same signal/register; besides, your code won't work as you expect.