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Still no reply.
I'll try to see if this has been corrected in the new 10.0 release of the QuartusII software
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Hi,
your problem is that you try to set some reg ( hazard, sample ) in different processes.
You have to put them together in one.
module design1 (
clock ,
reset ,
hazard ,
pulse
); // End of port list
//-------------Input Ports-----------------------------
input clock ;
input reset ;
input pulse ;
//-------------Output Ports----------------------------
output hazard ;
//-------------Input ports Data Type-------------------
// By rule all the input ports should be wires
wire clock ;
wire reset ;
//-------------Output Ports Data Type------------------
// Output port can be a storage element (reg) or a wire
reg [15:0] pulse_cntr;
reg pulse_reset;
reg [15:0] period_cntr;
reg [15:0] sample_value;
reg sample;
reg [23:0] result, result_ns;
reg [23:0] vt;
reg hazard;
initial begin
hazard = 1'b0 ;
end
always @ ( sample_value ) begin
result_ns = sample_value * 4'hc;
case ( result )
24'h00006c: vt = 24'hcccccc;
...
...
24'h7A1200: vt = 24'h320C80;
default : vt = 24'h0000;
endcase
if ( result_ns <= vt )
hazard = 1;
else
hazard = 0;
end
// Pulse Counter
always @(posedge pulse or posedge reset) begin
if ( reset == 1'b1 ) begin
sample_value <= 0;
pulse_cntr <=0;
hazard = 0 ;end
else if (sample == 1)
begin
sample_value <= pulse_cntr+1;
pulse_cntr <= 0;
sample <= 0;
end
else
begin
pulse_cntr <= pulse_cntr + 1;
end
end
// Period counter
always @(posedge clock or posedge reset) begin
if (reset == 1'b1)
begin
period_cntr <= 0;
sample <= 0;
hazard = 0 ;end
else if ( period_cntr == 16'h000f)//557300
begin
period_cntr <= 16'h0000;
sample <= 1;
end
else
begin
period_cntr <= period_cntr + 1;
end
end
always @(posedge clock or posedge reset) begin
if (reset == 1'b1)// begin
result <= 0;
else
result <= result_ns ;
end
endmodule // End of Module design
Kind regards
GPK
Honored Contributor
