Verilog: multiple conditions inside an if statement

1. Yes its fine. Remember, all those conditions create longer logic chains, reducing the max speed of your design

2. As many as you want. The limiting factor might be if it actually works at the desired clock speed.

3. Because you're trying to read more than one location per clock cycle, this is not a memory, but an array of registers. It cannot infer a memory as only a single address can be read/written per clock cycle.