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Honored Contributor
Honored ContributorVerilog: multiple conditions inside an if statement
I have a 2D memory i created. 7X16 size, Ii.e 5 rows 16 bit each. i have 2 8 bit data coming in, and i want to fill 5 rows of the memory with the data. first set of data will go automaticly t...
Altera_ForumHonored Contributor
Honored Contributor1. Yes its fine. Remember, all those conditions create longer logic chains, reducing the max speed of your design
2. As many as you want. The limiting factor might be if it actually works at the desired clock speed. 3. Because you're trying to read more than one location per clock cycle, this is not a memory, but an array of registers. It cannot infer a memory as only a single address can be read/written per clock cycle.
