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Altera_Forum's avatar
Altera_Forum
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12 years ago

Verilog modules

Hi all,

I have recently purchased a DE1 which I have been playing round with and attempting to learn Verilog. I have a question in regards to modules. Currently I am using the DE1 to emulate a gameboy cartridge using the code below (not working): 


module gameboycartridge (RD, WR, CS, ADDR, DATA);
    //Inputs 
    input RD;
    input WR;
    input CS;
    input  ADDR;
    
    //Outputs
    output  DATA;
    
    flash_rom rom (RD, ADDR, ADDR, DATA);
endmodule
module flash_rom (OE, CE, RM_ADDR, RM_DATA, FL_ADDR, FL_DQ, FL_OE_N, FL_WE_N, FL_RST_N);
    //Inputs 
    input OE;
    input CE;
    input  RM_ADDR;
    //Outputs
    output  RM_DATA;
    
    //Flash
    output  FL_ADDR;
    input  FL_DQ;
    output FL_OE_N;
    output FL_WE_N;
    output FL_RST_N;
    
    assign FL_OE_N = RD || ADDR;
    assign FL_WE_N = 1;
    assign FL_RST_N = 1;
    assign FL_ADDR = RM_DATA;
    assign RM_DATA = FL_DQ;
endmodule

It's a very basic example, just routing address lines to the onboard flash. I know why it doesn't work, (leaving ports unconnected when instantiating the flash_rom module). I had hoped that it might work that way such that I could say create another module that accessed the sram instead and abstract away from those details in the higher level module, just passing address, data and control signals to the module.

So my question is: Is there some way I can have a module that accesses ports not passed to it by a higher level module or is there some other way I can achieve it?

Any help appreciated.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    No. Most synthesis tools require that all signals data pass through a module port. Hierarchical references that avoid ports are not allowed in RTL coding styles.

    SystemVerilog has an interface construct that allows you to bundle up common signals in a single port declaration. This avoids repeated declaration and connection of signals.

    SystemVerilog also has a .* (dot-star) construct that automatically connect signals with ports having the same name.

    Suppose your flash_rom declaration looked like this: 

    module flash_rom (
    //Inputs 
    input OE,
    input CE,
    input  ADDR,
    //Outputs
    output  DATA,
    
    //Flash
    output  FL_ADDR,
    input  FL_DQ,
    output FL_OE_N,
    output FL_WE_N,
    output FL_RST_N
);
    
    assign FL_OE_N = RD || CS;
    assign FL_WE_N = 1;
    assign FL_RST_N = 1;
    assign FL_ADDR = RM_DATA;
    assign RM_DATA = FL_DQ;
endmodule
    Then your higher level module would look like this: 

    module gameboycartridge (
    //Inputs 
    input RD,
    input WR,
    input CS,
    input  ADDR,
    
    //Outputs
    output  DATA
//Flash
    output  FL_ADDR,
    input  FL_DQ,
    output FL_OE_N,
    output FL_WE_N,
    output FL_RST_N
);
 flash_rom rom (.OE(RD), .CS(ADDR),  .*);
endmodule