Verilog modules

No. Most synthesis tools require that all signals data pass through a module port. Hierarchical references that avoid ports are not allowed in RTL coding styles.

SystemVerilog has an interface construct that allows you to bundle up common signals in a single port declaration. This avoids repeated declaration and connection of signals.

SystemVerilog also has a .* (dot-star) construct that automatically connect signals with ports having the same name.

Suppose your flash_rom declaration looked like this:

module flash_rom (
    //Inputs 
    input OE,
    input CE,
    input  ADDR,
    //Outputs
    output  DATA,
    
    //Flash
    output  FL_ADDR,
    input  FL_DQ,
    output FL_OE_N,
    output FL_WE_N,
    output FL_RST_N
);
    
    assign FL_OE_N = RD || CS;
    assign FL_WE_N = 1;
    assign FL_RST_N = 1;
    assign FL_ADDR = RM_DATA;
    assign RM_DATA = FL_DQ;
endmodule

Then your higher level module would look like this:

module gameboycartridge (
    //Inputs 
    input RD,
    input WR,
    input CS,
    input  ADDR,
    
    //Outputs
    output  DATA
//Flash
    output  FL_ADDR,
    input  FL_DQ,
    output FL_OE_N,
    output FL_WE_N,
    output FL_RST_N
);
 flash_rom rom (.OE(RD), .CS(ADDR),  .*);
endmodule