verilog-module instantiation

actually module A do have inputs and outputs. I just didn't include them here because my main concern is on the module instantiation. I just want to show that the input to module B are defined. So just ignore the inputs and output of module A.

And, module B is not a register/RAM nor a flipflop...what i m trying to do is, i want to make module B a function, that i could call anytime i want, like in C language. Can it works this way? I did it wrong ?