verilog-module instantiation

As shown above, module A has no in- or ouputs. But there are undefined signals like s_in. I think. it's pointless to discuss the problem details at this level of information.

There are basically three possible reasons:

- missing simulation stimulus

- the output depends on the state of uninitialized internal signals, as discussed by BadOmen

- missing data path in the internal logic

As Rysc metioned, Modelsim has perfect means to trace where the unexpected ouput comes from.