verilog-module instantiation

I meant initialize registers/RAMs in the submodule. I see in module B you have some sort of net with sensitivity to 'start' but without seeing that net I have no clue what you have implemented. If your intent was to create a flipflop you should be driving it with a clock and reset as well and using an enable bit if you don't want it to capture every clock cycle. If you don't drive a reset into a register at the beginning of the simulation you'll get unknown data out of it (Modelsim can't assume high or low outputs from unitialized regs/RAMs). There are templates in Quartus II under the edit menu you can take a look at for typical hardware blocks such as registers, memory, etc...