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Altera_Forum's avatar
Altera_Forum
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14 years ago

verilog-module instantiation

hi all... currently working on a project, i have a top level module (module A), with a module instantiated in it ,module B. I just have one question. When does the system know when to start running m...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Is the output dependent on something that might not be initialized like a flip flop or RAM in module B?

Also I would double check signal widths in both modules to make sure signals are not getting truncated somewhere in your logic. I'm not sure if there is a way to check for this in Modelsim but the Quartus II synthesis engine should issue you a warning when this happens.