Verilog issue with case & assign statement

Hello,

I defined an assign and case statement in my code as following:

// NOT into a process

assign cf_data = cf_we_n ? cf_data_in : cf_data_out;

...

// State into a case statement, into a process.

CM_WR_DATA: begin

cf_we_n = 1'b0;

i_wr = i_wr + 1;

n_pin_control = CM_WR_WAIT;

end

It seems pretty short and easy, but I got an issue : my state CM_WR_DATA is done two times instead of one time, so my integer i_wr is incremented by 2. It is due to the assign statement. In fact, if I comment the assign statement, it works. By the same way, if I comment the cf_we_n, it works too. cf_data is not in the sensitive list of the process involved. I have only one state machine, so there isn't any conflicts.

So I tried to create a case state in addition:

CM_WR_DATA: begin

cf_we_n = 1'b0;

n_pin_control = CM_WR_ADDITIONNAL;

end

CM_WR_ADDITIONNAL: begin

i_wr = i_wr + 1;

n_pin_control = CM_WR_WAIT;

end

It doesn't fix my problem, i_wr is still incremented by 2.

Does sb have any ideas ?

Thanks !