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Altera_Forum
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15 years ago

Verilog issue with case & assign statement

Hello, I defined an assign and case statement in my code as following: // NOT into a process assign cf_data = cf_we_n ? cf_data_in : cf_data_out; ... // State into a case statement, ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

I doubt, if the problem can be found without knowing the complete process code. But in any case, I won't use non-blocking assignments in the process. It's, as a popular paper says, a coding style that kills.