Verilog design and RTL viewer (Quartus II 8.1)

Hi everyboy,

I am not used with verilog (telling the truth I'm not used in design in general :P ) and I have a question... I don't understand why some register i shown on the right and only one on the left in this simple counter

module counter (data, count, rco, load, enable, reset, clock);
	
parameter WIDTH=4;
input  data;
input load, enable, reset, clock;
output  count;
output rco;
wire  data;
wire rco, load, enable, reset, clock;	
reg  count;
assign rco = count == {WIDTH{1'b1}} ? 1'b1 : 1'b0;
	
always @ (posedge clock)
	begin
		if (!reset)
			count <= 0;
		else if (enable) begin
				if (load) count <= data;
				else count <= count + 1'b1;
			 end			
	end
endmodule 

There is a screenshot of RTL viewer.

img840.imageshack.us/img840/196/countera.jpg

(sorry i cant post as image ... forumm need 5 post :( )

Is there a problem? Some options are wrong? I use Quartus 8.1 because i like the integreted simulator, from version 9 there isn't right?

Thanks a lot in advance,

Alessandro Vincenzi