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Altera_Forum
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15 years ago

Verilog design and RTL viewer (Quartus II 8.1)

Hi everyboy, I am not used with verilog (telling the truth I'm not used in design in general :P ) and I have a question... I don't understand why some register i shown on the right and only one on...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The block placement in RTL and gate level netlists is arbitrary and doesn't have a particular meaning. Everything looks correct in your design.