m_kumar
Occasional Contributor
5 years agoverilog data latching.
Hi.
can anybody help to how to latch the data with different clock inputs (means: i'am getting an 12 bit data serially at 200Mhz clk input. i'm storing it in reg varialble, and i want use that 12bit data in 50Mhz clock source in another module).
Thanks.
regards