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Occasional Contributorverilog data latching.
Hi.
can anybody help to how to latch the data with different clock inputs (means: i'am getting an 12 bit data serially at 200Mhz clk input. i'm storing it in reg varialble, and i want use that 12bit data in 50Mhz clock source in another module).
Thanks.
regards
3 Replies
KennyT_alteraSuper Contributor
you may use set multi cycle clock for this type of requirement. You can refer to https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/analyze/sta/sta_db_set_multicycle_path.htm
m_kumarThank you so much sir. i'm done with the task.
Thanks for valuable feedback
- KennyT_altera
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