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m_kumar's avatar
m_kumar
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

verilog data latching.

Hi. can anybody help to how to latch the data with different clock inputs (means: i'am getting an 12 bit data serially at 200Mhz clk input. i'm storing it in reg varialble, and i want use that 12...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago

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