Verilog code

hi everyone.

Please suggest me what went wrong in my test bench code its getting simulated but the problem is with its waveform as I am new to verilog, I am not getting the problem.

Thank you in advance.

`timescale 1ns/100ps

module state_text;

reg clk;

reg rst;

reg x;

reg y;

reg z;

reg qa;

reg qb;

state hi(.clk(clk),.rst(rst),.x(x),.y(y),.z(z),.qa(qa),.qb(qb));

initial begin

x=1'b0;

y=1'b0;# 2

x=1'b0;

y=1'b1;# 2

x=1'b1;

y=1'b0;# 2

x=1'b1;

y=1'b1;

end

endmodule