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Altera_Forum
Honored Contributor
Honored ContributorVerilog code
hi everyone. Please suggest me what went wrong in my test bench code its getting simulated but the problem is with its waveform as I am new to verilog, I am not getting the problem. Thank you...
Altera_ForumHonored Contributor
Honored ContributorWhat's the problem? Did you mean to only produce a waveform for y and x? What about the clock and rest?
