Verilog Code Error: Counter : Read and writer through PIO

 module Counter_Top_Level_design   
 (
  input clk,
  output reg[7:0] out
 );
always @(posedge clk) 
begin
 out <= out + 1;
end
 
NIOS_SYSTEM niosii_system_inst (
		.clk_clk           (clk ),					//        clk.clk
		.reset_reset_n     (rst_n ),					//      reset.reset_n
		.counter_out_export (out)
	);
 
endmodule

I have assigned PIO (output):8 bit, its showing error. If i assign PIO (input):8 bit error not coming. But i want to read the counter data.