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Honored Contributor

9 years ago

Verilog Assignment

Hi all,

I have a very basic question, I think.

I develop in VHDL but in this moment I have to port a Verilog crunk of code.... the problem is that I don't know the Verilog... :( !

Can anyone help me to understand this assignment (conditional statement I presume):

module xxx(
    .
    .
   input   z,
    .
    .
);
wire x;
reg  y;
assign x = y == z;
.....

Thank you

2 Replies

Altera_Forum
Honored Contributor
9 years ago
This is logically equivalent to:

if (y == z)
x = 1;
else
x =0;

A clearer way to write it would have been:

assign x = (y == z); // x assigned result of Boolean equality comparison

or

assign x = (y == z) ? : 1'b1 : 1'b0; // Called a conditional assignment in verilog
Altera_Forum
Honored Contributor
9 years ago
--- Quote Start ---
This is logically equivalent to:

if (y == z)
x = 1;
else
x =0;

A clearer way to write it would have been:

assign x = (y == z); // x assigned result of Boolean equality comparison

or

assign x = (y == z) ? : 1'b1 : 1'b0; // Called a conditional assignment in verilog
--- Quote End ---

Thank you very much.