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Altera_Forum
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9 years ago

Verilog Assignment

Hi all, I have a very basic question, I think. I develop in VHDL but in this moment I have to port a Verilog crunk of code.... the problem is that I don't know the Verilog... :( ! Can anyone h...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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This is logically equivalent to:

if (y == z)

x = 1;

else

x =0;

A clearer way to write it would have been:

assign x = (y == z); // x assigned result of Boolean equality comparison

or

assign x = (y == z) ? : 1'b1 : 1'b0; // Called a conditional assignment in verilog

--- Quote End ---

Thank you very much.