Forum Discussion
VerilogStudent
New Contributor
New ContributorVerilog - Mealy To Moore And State Diagram
Hey, i got a question and i want to know if i did right.
This is the Verilog code and i need to show the state diagram. this is what i did.
THE CODE
And this is the state. I think.
...
Ok i see. And i`m doing this because this is the work we asked to do.
So i added the Moore Diagram, is this ok? and now i can convert it?
sstrell
Super Contributor
Super ContributorNo, I mean you shouldn't have two identical entries in a case statement (two s1, two s2, two s3).
But as I said, there's no good way to fix this because the basic design is inherently a Mealy machine. What is your goal here and why do you want to change it into a Moore machine?
#iwork4intel
VerilogStudentNew Contributor
New ContributorOk i see. And i`m doing this because this is the work we asked to do.
So i added the Moore Diagram, is this ok? and now i can convert it?
