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VerilogStudent's avatar
VerilogStudent
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5 years ago
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Verilog - Mealy To Moore And State Diagram

Hey, i got a question and i want to know if i did right. This is the Verilog code and i need to show the state diagram. this is what i did. THE CODE And this is the state. I think. ...
  • VerilogStudent's avatar
    VerilogStudent
    5 years ago

    Ok i see. And i`m doing this because this is the work we asked to do.

    So i added the Moore Diagram, is this ok? and now i can convert it?

VerilogStudent's avatar
VerilogStudent
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5 years ago

What do you mean by "two matching entries"? you mean when i write

begin y = 0

and then y=1 for example? if does, how can i fix it?

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

No, I mean you shouldn't have two identical entries in a case statement (two s1, two s2, two s3).

But as I said, there's no good way to fix this because the basic design is inherently a Mealy machine. What is your goal here and why do you want to change it into a Moore machine?

#iwork4intel

  • VerilogStudent's avatar
    VerilogStudent
    Icon for New Contributor rankNew Contributor
    5 years ago

    Ok i see. And i`m doing this because this is the work we asked to do.

    So i added the Moore Diagram, is this ok? and now i can convert it?