Forum Discussion
New ContributorVerilog - Mealy To Moore And State Diagram
Ok i see. And i`m doing this because this is the work we asked to do.
So i added the Moore Diagram, is this ok? and now i can convert it?
Super ContributorLooking at your Moore code, you shouldn't have two matching entries in a case statement, which Verilog might let you get away with, but you shouldn't do it.
But the design is inherently a Mealy state machine (dependent on the state and x), so I'm not sure why you want/need to turn it into a Moore machine.
#iwork4intel
New ContributorWhat do you mean by "two matching entries"? you mean when i write
begin y = 0
and then y=1 for example? if does, how can i fix it?
- sstrell
No, I mean you shouldn't have two identical entries in a case statement (two s1, two s2, two s3).
But as I said, there's no good way to fix this because the basic design is inherently a Mealy machine. What is your goal here and why do you want to change it into a Moore machine?
#iwork4intel
- VerilogStudent
Ok i see. And i`m doing this because this is the work we asked to do.
So i added the Moore Diagram, is this ok? and now i can convert it?
