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Altera_Forum's avatar
Altera_Forum
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17 years ago

Using internal tri-state signals in bus systems

I'm writing a simple bus system, and I'm using internal tri-state signals for the data out bus (that converts to muxes, or something similar). So far so good.

The problem is the read ack signal. I want a simple or-logic that allows me to ack a bus read from serveral entities. The first attempt was to set RDACK <= 'L' when idle, but this is not (properly?) implemented in quartus, since it seems do work like '0'. Setting RDACK <= 'Z' yields no error, but it sets the entire bus constantly high (from a tool point of view this makes sense: no entity will ever drive '0' on the line, thus it can be set as constantly high).

I can provide additional information, but this seems like a standard problem that should have a standard soloution. I dont feel like cluttering up my design with a huge or-gate if I dont have to...

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    If I have well understood your problem, you would like to avoid that the bus is held high while waiting for a read ack. While keeping your setting RDACK <= 'Z' you can use an external pull-down resistor to keep the bus low. So you don't need a huge OR gate to read an ack signal in your bus.

    Is this OK for you?
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Do I understand right that you are talking of an internal (virtual) wired-or bit bus? So the said huge or-gate would be synthesized at gate level anyway, it's just a matter of convenience trying to use a wired-or in the HDL representation.

    I fear, that the HDL compilers have no means to represent an internal wired or. The VHDL Standard VHDL Synthesis Package specification (1076.3) tells, that a synthesis tool shall interpret the forcing and weak values both as logic 0 and 1, respectively (Clause 4.3.1). Consequently, Quartus regards a 'L' and a '1' driving the same signal as multiple source error.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Sorry for beeing a bit unclear, after all it was very late....

    Yes FvM, this is exactly my problem. In hardware, the or gate will exist either way, but having it hidden in a virtual tri-state signal would look better on the schematics.

    Maybe there is a megawizard function for this?