Using internal tri-state signals in bus systems

Do I understand right that you are talking of an internal (virtual) wired-or bit bus? So the said huge or-gate would be synthesized at gate level anyway, it's just a matter of convenience trying to use a wired-or in the HDL representation.

I fear, that the HDL compilers have no means to represent an internal wired or. The VHDL Standard VHDL Synthesis Package specification (1076.3) tells, that a synthesis tool shall interpret the forcing and weak values both as logic 0 and 1, respectively (Clause 4.3.1). Consequently, Quartus regards a 'L' and a '1' driving the same signal as multiple source error.