Altera_Forum
Honored Contributor
14 years agoUsing assert() report in VHDL
Hello!
I'm trying to use command assert(...) report "..." in Quartus 9.1 to debug my project. I've tested different combinations of this command according to the literature in the Internet, but cannot see my report message anywhere. Should I check some options in Quartus or where exactly this message should appear? P.S. I'm using standard simulation tool. Thanks!