Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Using assert() report in VHDL

Hello! I'm trying to use command assert(...) report "..." in Quartus 9.1 to debug my project. I've tested different combinations of this command according to the literature in the Internet, but...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Try this in your code somewhere:

process

begin

wait for 10 us;

assert false

report "Simulation complete!"

severity failure;

end process;

This process will end your simulation after 10 us. See if the message shows up somewhere. If not, try to learn to use Modelsim. Its a much nicer simulation tool.

Cheers,

Dave