Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Using assert() report in VHDL

Hello! I'm trying to use command assert(...) report "..." in Quartus 9.1 to debug my project. I've tested different combinations of this command according to the literature in the Internet, but...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

In Verilog, the assert messages only started to appear with Quartus 10.0.

Maybe try to update ?