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Altera_Forum's avatar
Altera_Forum
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17 years ago

Use of permanently enabled tristate buffer

Hi,

On an existing design, I've seen a gated clock output being buffered at the pin with a 'SOFT' buffer in series with a permanently enabled tristate buffer. As I am not familar with this arrangement, can anybody explain why this might have been tackled in this manner?

Thanks,

Tim

Note: The 'soft' and 'tristate' buffers in this design appear on a schematic entry diagram driving an output pin.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    You get a permanently enabled tristate buffer, if a signal is defined as inout but only used as output. Quartus isues a warning to remind you, that something may have been forgotten in the design definition.