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BDarji's avatar
BDarji
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Usage of negative edge trigger for dual clock RAM

Dear all, Greetings of the Day! We are having one dual port RAM with separate clock for port A and Port B. Port B related signals are driven within FPGA. While port A related signals will be driven...
Hdl
Timing
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

Based on timing reports it should be fine to use negedge trigger as you proposed.

I've also done RTL simulation and it works as expected.

Posedge:

Negedge:

Regards,

Nurina

  • BDarji's avatar
    BDarji
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Hello Nurina,

    Thank you for your response.

    Kind Regards,

    Bhaumik