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abhishek_nallur's avatar
abhishek_nallur
Icon for New Contributor rankNew Contributor
5 months ago

Understanding timing constraints in timing analyzer

Hi all,

I am quite new to timing constraints. I took an example code to understand and apply the constraints from FPGA Academy website.

https://fpgacademy.org/tutorials.html

Using the Quartus Prime Timing Analyzer VHDL code.

I am using Quartus prime lite 24.1 edition. FPGA 10M08DAF484C8G. I dont have any board.

As per tutorial i have added this constraint. 4ns = 250mhz clock

Still there is setup violations. How can i solve this?

I reduced the clock from 250 to 125 then the violation disappered.

What if i had a clock osc from outside the board with fixed 250mhz? Then how would i resolve the violations?

How to remove unconstrained i/o port paths also?

Any example codes, tutorials, explanation will be grateful.

Thank you

Timing

5 Replies

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    5 months ago

    Hi OP,


    We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.

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  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    5 months ago

    Thank you sstrell for answering.


    Hi OP,

    I believe sstrell has answered your inquires, do you able to close timing with your project?


    Regards,

    Richard Tan


    • FvM's avatar
      FvM
      Icon for Super Contributor rankSuper Contributor
      5 months ago

      Hi,
      I agree that the design should be fully constrained so that timing analyzer doesn't report unconstrained pathes any more.
      It's however rather unlikely that reported timing violations are caused by unconstrained IO. Consider a design with only asynchronous IO, it doesn't need specific IO constraints other than setting all IO to false_path. FPGA core logic will still violate timing if combinational delay between registers is too large. It can be only solved by restructuring logic, e.g. adding pipeline registers. Even in a partly unconstrained design, timing analyzer can show you why certain pathes fail timing closure.

      • sstrell's avatar
        sstrell
        Icon for Super Contributor rankSuper Contributor
        5 months ago

        Agreed.

        Another solution may be to just create virtual pin assignments for all I/O. Then the design is basically self contained in the device.

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    5 months ago

    A number of things here but the main thing is that you need to fully constrain the design first before you can rely on any timing reports. This training discusses the creation of I/O timing constraints: https://learning.intel.com/Developer/learn/courses/841/intelr-quartusr-prime-pro-software-timing-analysis-part-4-io-interfaces

    Once your design is fully constrained, then you can run setup and hold summary reports to verify whether the design meets timing.