Forum Discussion
abhishek_nallur
New Contributor
1 year agoUnderstanding timing constraints in timing analyzer
Hi all, I am quite new to timing constraints. I took an example code to understand and apply the constraints from FPGA Academy website. https://fpgacademy.org/tutorials.html Using the Quartus Prim...
sstrell
Super Contributor
1 year agoA number of things here but the main thing is that you need to fully constrain the design first before you can rely on any timing reports. This training discusses the creation of I/O timing constraints: https://learning.intel.com/Developer/learn/courses/841/intelr-quartusr-prime-pro-software-timing-analysis-part-4-io-interfaces
Once your design is fully constrained, then you can run setup and hold summary reports to verify whether the design meets timing.