Understanding timing constraints in timing analyzer

Hi,
I agree that the design should be fully constrained so that timing analyzer doesn't report unconstrained pathes any more.
It's however rather unlikely that reported timing violations are caused by unconstrained IO. Consider a design with only asynchronous IO, it doesn't need specific IO constraints other than setting all IO to false_path. FPGA core logic will still violate timing if combinational delay between registers is too large. It can be only solved by restructuring logic, e.g. adding pipeline registers. Even in a partly unconstrained design, timing analyzer can show you why certain pathes fail timing closure.