undefined clock in synthesis

Hi,

so i created a ram block in Quartus with megafunction wizzard. It is a 2-port MK4, i set it to auto, but it came out to be MK4. So it has one read, one write port, wren, clk, and addresses for read and write. I needed two of those for single-cycle: data memory and instruction memory, but i made only one component although in test bench i have 2 DUTs. Compiles fine with no warnings/errors. Source runs fine with these warnings:

# ** Warning: Warning: READ_DURING_WRITE_MODE_MIXED_PORTS is assumed as OLD_DATA

# Time: 0 ns Iteration: 0 Instance: /tb_cpu/dut3/altsyncram_component

# ** Warning: Warning: Port B will take the address_reg_b parameter as

reference clock source for Port B, which is CLOCK0

# Time: 0 ns Iteration: 0 Instance: /tb_cpu/dut3/altsyncram_component

# ** Warning: Warning: READ_DURING_WRITE_MODE_MIXED_PORTS is assumed as OLD_DATA

# Time: 0 ns Iteration: 0 Instance: /tb_cpu/dut2/altsyncram_component

# ** Warning: Warning: Port B will take the address_reg_b parameter as

reference clock source for Port B, which is CLOCK0

# Time: 0 ns Iteration: 0 Instance: /tb_cpu/dut2/altsyncram_component

so i dug altera documentation but it was not very informative.

When i run SYNTHESIZED version of design in modelsim, i get a bunch of undefines, including the CLOCK! i am not sure what is going on. Should i have created two separate components of ram even though they are the same? instead of having 1 component and 2 instances of it?

Thanking you in advance.